LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.

By: HACHTEL, GARY. DContributor(s): SOMENZI, FABIOMaterial type: Text

TextLanguage: ENGLISH Publication details: NEW DELHI ; SPRINGER (INDIA) PVT. LTD. Edition: 2006Description: 567Subject(s): LOGIC SYNTHESISDDC classification: 621.317.317 |

Average rating: 0.0 (0 votes)

Holdings
Item type	Current library	Home library	Call number	Status	Notes	Date due	Barcode
Reference	PCCOE	PCCOE	621.317.317 (Browse shelf(Opens below))	Available	E AND TC		PCCOEEC10323

Previous	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	No cover image available No cover image available	Next
Previous	621.317.317 MULTIRATE SYSTEMS AND FILTER BANKS.	621.317.317 FUNDAMENTALS OF POWER ELECTRONICS.	621.317.317 DIGITAL SIGNAL PROCESSING WITH FIELD PROGRAMMABLE GATE ARRAYS.	621.317.317 LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS.	621.317.317 POWER ELECTRONICS AND MOTOR DRIVES : ADVANCES AND TRENDS.	621.317.317 SENSORS AND TRANSDUCERS.	621.317.317 DIGITAL SIGNAL PROCESSING WITH FIELD PROGRAMMABLE GATE ARRAYS.	Next

There are no comments on this title.

to post a comment.